1. Field of the Invention
This invention relates generally to the cell structure, device configuration and fabrication process of power semiconductor devices. More particularly, this invention relates to a novel and improved cell configuration and processes to manufacture MOSFET device with embedded Schottky diodes in the same cell such that integrated cells with spacing savings and lower capacitance and higher performance are achieved.
2. Description of the Related Art
Conventional technologies for high efficiency DC/DC applications, a Schottky diode are usually added externally in parallel to a semiconductor power device, e.g., a power MOSFET device. FIG. 1A is a circuit diagram that illustrates the implementation of a Schottky with a power MOSFET device. The Schottky diode (SKY) is connected in parallel to the MOSFET device with a parasitic PN body diode to function as a clamping diode to prevent the body diode from turning on. In order to achieve higher speed and efficiency, once the parasitic P/N diode is turned on, both the electron and hole carriers are generated and that would require longer time to eliminate the carriers by electron-hole combination while the Schottky Diode is single carrier, i.e., electron carrier only and that can be drawn simply by the drain Electrode. The requirement for the clamping effect is that the Forward Voltage of the Schottky diode Vf is less than the parasitic PN diode (˜0.7V). As the electronic devices become more miniaturized, there are requirement to integrate the Schottky diode as part of the semiconductor power device as an IC chip to reduce the space occupied by the Schottky diode instead of connecting the Schottky diode as an external electronic component.
FIG. 1B is a cross sectional view of a trenched MOSFET device integrated with trench Schottky diodes as that disclosed by U.S. Pat. No. 6,351,018. The configuration as disclosed in the patented invention has a disadvantage that the Schottky diodes occupy additional space that is about the same space as the MOSFET. The trench Schottky diodes further suffer from a high leakage between the drain and source due to the increase in the phosphorus dopant concentration in the channel region during the sacrificial and gate oxidation processes. Furthermore, the device as shown has a higher capacitance due to the presence of the trench MOS-Schottky structure which has inherent parasitic capacitance from trench sidewall and bottom in trench MOS-Schottky as shown in left side of the cross section view in FIG. 1B.
In U.S. Pat. No. 6,433,396, a trench MOSFET device with a planar Schottky diode is disclosed as that shown in FIG. 1C. The configuration again has an advantage that the planar Schottky diode occupies additional space. Also, the formation process requires additional contact mask for the Schottky diode thus increases the cost and processes complications for producing the MOSFET power device with Schottky diode.
In U.S. Pat. No. 6,998,678 discloses another trench semiconductor arrangement as shown in FIG. 1D with a MOS transistor which has a gate electrode, arranged in a trench running in the vertical direction of a semiconductor body, and a Schottky diode which is connected in parallel with a drain-source path (D-S) and is formed by a Schottky contact between a source electrode and the semiconductor body. Again, the configuration has the same disadvantage that the Schottky diodes occupy additional space thus limiting the further miniaturization of the device. Furthermore, the manufacturing cost is increased due to the requirement that an additional P+ mask is required to form the Schottky diodes.
Therefore, there is still a need in the art of the semiconductor device fabrication, particularly for design and fabrication of the trenched power device, to provide a novel cell structure, device configuration and fabrication process that would resolve these difficulties and design limitations. Specifically, it is desirable to provide more integrated semiconductor power devices with embedded Schottky diode that can accomplish space saving and capacitance reduction such that the above discussed technical limitations can be resolved.